Abstract

FinFET, now firmly established in leading VLSI industries for their superior performance, exhibit heightened aging susceptibility that poses significant reliability challenges. The aggressive scaling of technology nodes has further compromised circuit reliability in recent years, highlighting the need for effective aging mitigation techniques. Recent advancements in the miniaturization of nanoscale technology have demonstrated the potential of optimizing performance parameters in standard cells using machine learning models and optimization algorithms through device sizing modifications. Building on this progress, we propose a methodology for optimizing performance parameters in 16nm high-performance (HP) FinFET for the first time. The approach leverages a multi-objective optimization algorithm framework to mitigate aging impacts across PVT variations while addressing NBTI and HCI effects by optimally adjusting FinFET design parameters, including channel length (lg), width (tfin), and height (hfin). With SPICE simulations, time-series datasets were generated to train machine learning models that achieved an R² score exceeding 0.99 and a mean absolute percentage error below 1% across standard cells. Our approach yields a significant simulation speedup and a reduction in simulation workload compared to traditional SPICE simulations. Using the proposed optimization algorithm framework, we improved the power-delay product (PDP) by up to 36.97% under non-aging conditions and 34.94% with aging considered with respect to the nominal dimension at the fresh year, demonstrating significant performance gains for FinFET-based standard cells. The experimental results on 12 distinct complex cells validate the aging mitigation across years.

Abstract

Globesity has widely affected the world population. It is a multifactorial health problem. Obesity can be caused by high-fat intake, high-calorie intake, physical inactivity, age, gender, or hormonal issues that can induce many health issues, such as cardiovascular disorders, diabetes, and metabolic disorders. Health facilities are insufficient to provide services to the whole population. In such a case, introducing Artificial Intelligence (AI) in the health sector is one of the most significant steps that can be taken. With the help of AI, the prognosis, diagnosis, and treatment can be provided to individuals within their homes and setups without any physical interactions. Assembling the data collected with AI can help to give more information on the type of obesity prevailing in a particular society so that it could be prevented in the population. Since AI learning is relatively novel within the existing system of medicine, enabling …

Abstract

A method for describing, distributing and re-producing specifications of analog IC using AI models, is fulfilled in the ongoing description by (a) creating an AI model to represent the electrical specifications of the analog integrated circuit over a specified range of PVT, input and output loading, and aging conditions,(b) training the AI model with simulation data associated with the analog IC, wherein the simulation inputs include a plurality of instances of PVT (Process, Voltage, Temperature), input/output loading, and aging conditions,(c) electronically enabling peripheral functions with the AI model into an AI model pack, wherein the peripheral functions include a set of computer code modules to extract the AI model, perform user requested operations, calculate specifications of the analog IC on-the-fly and interact with the user, and (d) distributing the encrypted AI model pack to a plurality of users.

Abstract

This paper explores advanced voltage reference designs with extremely low power consumption, specifically under one microwatt. These designs are crucial for portable electronic systems that rely on minimal power. The paper categorizes these voltage references based on the types of devices used to generate temperature-proportional or complementary signals. It also provides key design examples to illustrate these concepts. Additionally, the paper enhances understanding by conducting a comparative analysis of performance metrics, including power consumption, temperature coefficient, physical size, and resistance to variations in the manufacturing process.

Abstract

This paper presents a dual-loop reference-less Clock and Data Recovery (CDR) architecture implemented in TSMC 28nm CMOS process for PCIe Gen4 application. A novel frequency detector (FD) with a wide frequency acquisition range is presented, which avoids harmonic locking issues and is independent of input transition density. The FD demonstrates rapid locking capabilities, securing synchronization with Pseudo-Random Binary Sequences (PRBS7 and PRBS31) data patterns. The locking time from PCIe Gen1 (2.5Gbps) to PCIe Gen4 (16Gbps) is less than 5us. The CDR achieves a power consumption of less than 2mW with a supply voltage of 0.9V.

Abstract

The heightened sensitivity of circuit behavior to manufacturing processes is surging in sub-nanometer nodes, presenting a formidable challenge for high-dimensional performance modeling. Estimating circuit performance variations resulting from process randomness in upcoming technology nodes aids in implementing appropriate countermeasures to handle them. Addressing this, we introduce a multi-node transfer learning method for predicting the performance of VLSI digital circuits. The proposed method facilitates Zero-shot Learning in future technology nodes based on insights gained from analyzing the circuit’s process-induced behavior in established nodes. The approach is fast, scalable, and robust, leveraging digital standard cell characterization that can be applied to estimate the performance of a wide array of intricate circuits. Experimental results affirm the approach’s exceptional data efficiency, achieving a speed increase of up to 104 times, all the while maintaining superior accuracy compared to traditional simulators.

Abstract

Analog circuit characterization is a pivotal phase in the design process, serving to validate their performance. It ensures that design choices lead to optimization, ultimately resulting in reliable and robust designs. The conventional, resource-intensive circuit characterization using traditional simulation tools is being supplanted by Machine Learning surrogate models, providing computational advantages. Nevertheless, these models tend to be specific to particular circuits, demanding significant design efforts and often lacking reusability for other designs and topologies. In this paper, we introduce a Unified Neural Network Architecture that is versatile and computationally efficient. It offers a streamlined and effective approach for modeling a diverse array of analog circuits prone to process, voltage, and temperature variations. Experimental trials conducted on various circuits in CMOS 180nm, 65nm and 28nm technologies demonstrate a mean average percentage error of less than 1%, affirming the effectiveness and reusability of the proposed architecture. This leads to substantial savings in design time, computational resources, and characterization costs.

Abstract

Modeling process, operating condition, reliability, and technological variation in transistor level design introduce significant variance in device and performance parameters. This paper presents a machine-learning-based architectural approach that enhances model performance, as a step towards developing Foundation Models tailored for circuit data, accurately capturing technology and process-induced variations in leakage power, voltage, and current. The architecture incorporates the impact of varying operating conditions, including temperatures from -55°C to 125°C and supply voltage fluctuations of ±10% on 16nm HP FinFET, and 16nm, 22nm, 32nm, and 45nm HPMGK CMOS technology nodes. By enhancing the performance of baseline machine-learning models using a chained architecture to cater to the high variance in target, our C-Arch serves as a versatile framework for circuit modeling when the data spread is high. Experimental results on current, voltage, and leakage power estimation, demonstrate average improvements of up to 93.76%, 96.17%, and 88.82% in Mean Absolute Percentage Error compared to baseline models, underscoring the computational savings and viability of Foundation Models in circuit design.

Abstract

One-class classification (OCC) is a machine learning technique employed in scenarios involving imbalanced data, limited labeled data, or the need to detect anomalies or novel patterns. One-Class Classification by Ensembles of Regression (OCCER) models have shown excellent performance for OCC problems. In this paper, we study whether the combinations of ensemble methods such as random subspace and random projection with OCCER can be used to improve the performance of OCCER. Our main objective is to explore the impact of diversity creation methods, including bagging, random subspace, and random projections, on enhancing the performance of the OCC ensemble method. Additionally, we investigate the feasibility of applying the OCCER ensemble method to a novel low-dimensional space generated by autoencoders, all while maintaining high prediction accuracy. The experimental results over 37 datasets demonstrate that the creation of diverse OCCER models using random subspace and random projection substantially improves the performance of the OCCER. The diversity creation method, Random subspaces, outperforms other diversity creation methods.

Abstract

Voltage-Controlled Oscillator (VCO) is a crucial component of a Phase-Locked Loop (PLL) system. However, the frequency of a typical Ring-Oscillator-based VCO varies by about 2–3 times across its frequency tuning range and process, voltage and temperature (PVT) conditions. The gain of a Ring-VCO is another crucial parameter that is significantly affected by PVT variations, thereby impacting the stability and loop bandwidth of the PLL. This paper describes a compensation technique to minimize variations in Ring-VCO gain across PVT conditions. A Charge-Pump PLL operating at 4 GHz is implemented in a 28nm CMOS process. The gain of the Ring-VCO varies by ±27% across PVT at 4 GHz. This gain variation of Ring-VCO combined with other PVT-dependent blocks of PLL lead to a deviation of ±60% in Loop Bandwidth and ±21 % in Phase-Margin (PM). Process trimming reduces the VCO gain variation to ±25 %. Subsequently, the temperature compensation technique reduces the VCO gain variation by 3 times to ±8 %, over a temperature range −40∘C to 125∘C . The resulting variations in Loop Bandwidth and Phase-Margin are reduced to ±34%” and ±l5%” respectively.