Abstract

One-class classification (OCC) is a machine learning technique employed in scenarios involving imbalanced data, limited labeled data, or the need to detect anomalies or novel patterns. One-Class Classification by Ensembles of Regression (OCCER) models have shown excellent performance for OCC problems. In this paper, we study whether the combinations of ensemble methods such as random subspace and random projection with OCCER can be used to improve the performance of OCCER. Our main objective is to explore the impact of diversity creation methods, including bagging, random subspace, and random projections, on enhancing the performance of the OCC ensemble method. Additionally, we investigate the feasibility of applying the OCCER ensemble method to a novel low-dimensional space generated by autoencoders, all while maintaining high prediction accuracy. The experimental results over 37 datasets demonstrate that the creation of diverse OCCER models using random subspace and random projection substantially improves the performance of the OCCER. The diversity creation method, Random subspaces, outperforms other diversity creation methods.

Abstract

Voltage-Controlled Oscillator (VCO) is a crucial component of a Phase-Locked Loop (PLL) system. However, the frequency of a typical Ring-Oscillator-based VCO varies by about 2–3 times across its frequency tuning range and process, voltage and temperature (PVT) conditions. The gain of a Ring-VCO is another crucial parameter that is significantly affected by PVT variations, thereby impacting the stability and loop bandwidth of the PLL. This paper describes a compensation technique to minimize variations in Ring-VCO gain across PVT conditions. A Charge-Pump PLL operating at 4 GHz is implemented in a 28nm CMOS process. The gain of the Ring-VCO varies by ±27% across PVT at 4 GHz. This gain variation of Ring-VCO combined with other PVT-dependent blocks of PLL lead to a deviation of ±60% in Loop Bandwidth and ±21 % in Phase-Margin (PM). Process trimming reduces the VCO gain variation to ±25 %. Subsequently, the temperature compensation technique reduces the VCO gain variation by 3 times to ±8 %, over a temperature range −40∘C to 125∘C . The resulting variations in Loop Bandwidth and Phase-Margin are reduced to ±34%” and ±l5%” respectively.

Abstract

A method and system based on machine learning to create self-adapting analog circuits adapted to change their internal components on-the-fly in response to changes in process, voltage, and temperature to re-tune the electrical characteristics back to nominal specified values is disclose. The method and system herein comprise of designing the analog circuit, generating simulation data for machine learning, creating a full query database, creating and training, using simulation results, a machine learning (ML) model of the circuit and applying the ML model to infer the required changes to internal components of the analog circuit in response to changes in P, V, and T conditions. With this method and system, evaluation of the adverse effects of PVT changes, decision on internal circuit changes, and realization of requisite design changes are performed by the computer system solely within a ML data domain

Abstract

Low Quiescent Current, Capacitor-Less LDO with Adaptively Biased Power Transistors and Load Aware Feedback Resistance

Abstract

This paper presents a sub-1V, 593 pA current reference without using resistors and amplifiers. Temperature compensation is achieved by incorporating a CTAT gate to source voltage and a PTAT drain to source voltage in an NMOS-based sub-threshold biased circuit. The proposed architecture achieves process variation of ±0.75%, which enables seamless trim-free operation. Implemented in the 90nm CMOS process, the temperature-compensated current reference achieves a temperature coefficient of 378 ppm/°C over a high-temperature range of −40 to 100°C and a line sensitivity of 0.198%/V in a supply voltage range from 0.8 to 2.5 V. Duty cycling technique is adopted in the CTAT generator to reduce the total average power consumption. The proposed circuit occupies an area of 0.074 mm 2 while consuming only 3.3 nW at a typical corner of 27 °C and 0.8 V supply.

Abstract

The prevalence of MOSFETs in diverse electronic applications highlights their significance. However, the sensitivity of MOSFET threshold voltage to process variation poses a substantial challenge in achieving consistent device performance. This paper proposes a novel approach to overcome this challenge by employing a threshold voltage (VTH) tracking circuit that tracks the variation in VTH. Our primary objective is to develop a current reference that remains invariant across process, voltage, and temperature (PVT) variations, eliminating the need for an external trimming circuit. This is achieved by the meticulous integration of VTH tracking circuit, CTAT generator, PTAT generator, and a current adder. By employing this design,a process variation (σ/µ) of 0.48%, a temperature coefficient (TC) of 210ppm/ ◦C for a temperature range of −40◦C to 120◦C, and a line sensitivity of 1.6% is achieved over a voltage range of 1.6V − 3V. The proposed circuit occupies an area of 0.013mm2 while consuming power of 56µW at a typical corner of 27◦C and a supply of 1.8V. The given circuit is implemented in a 180nm CMOS process node with a generated reference current of 61nA.

Abstract

This paper presents a new approach to efficient process monitor (PMON) design. It focuses on robust process tracking of PMOS and NMOS devices while minimizing the effects of external factors such as die temperature variations and local supply voltage changes. The proposed design method introduces a comprehensive set of PMON libraries tailored for the specific device types provided by a target technology node. Central to this method is a novel design automation routine based on Zero Temperature Coefficient (ZTC) biasing of a ring oscillator-based PMON. This work demonstrates the effectiveness and scalability of the proposed method across multiple process nodes. The generated PMON structures show a multi-fold improvement in sensitivity for process tracking compared to current state-of-the-art solutions.

Abstract

This paper presents a low-voltage, low-power PVT-invariant voltage reference with excellent line sensitivity for IoT and biomedical applications. By applying a bias current in an NMOS-based composite pair and bias voltage at the body of NMOS to get the temperature-compensated voltage reference over a wide temperature range. The proposed design implemented in a 180nm CMOS process gives an output of 141mV which is independent of process, voltage, and temperature. Without trimming, the process variation of the proposed design is 0.988% , and the temperature coefficient of the proposed voltage reference is over a wide temperature range of to . For a supply voltage ranging from 0.6V the line sensitivity of the reference is 0.0012%N.

Abstract

Designing robust performance models for modern complex digital circuits in the face of rapidly accelerating process variations is a critical yet demanding task. This paper introduces an efficient statistical performance modeling approach for VLSI digital circuits that incurs minimal computational expense. The fundamental concept involves capitalizing on knowledge gained from circuit modeling in one technology node to streamline the modeling process in another. This is achieved by merging previously established statistical models of process technology with a limited set of simulation data from a subsequent process technology through transfer learning. Comprehensive experiments conducted across diverse technology nodes demonstrate that the proposed framework is robust, precise, efficient in data usage, and computationally superior to other cutting-edge performance modeling techniques.

Abstract

This paper introduces an ultra-low-power RC oscillator that utilizes a resistance amplification technique. The resistance amplifier achieves the effect of a large resistance by amplifying the I-V characteristics of a small resistance, resulting in significant area savings. To improve precision in oscillation frequency, a continuous time auto-zeroing technique is incorporated to dynamically calibrate the offset voltage of an integrated amplifier. Fabricated using a 180−nm CMOS process, the designed oscillator produces a 100−Hz clock signal while consuming only 2 nW power under compact silicon area (0.12mm2). Additionally, it achieves a competitive temperature coefficient (TC) of 280ppm/∘C and line sensitivity (LS) of 1.1 % / V without the need for any calibration.