Abstract

The paper presents a 0.5 V, ultra-low power current, and voltage reference circuit in a single block, giving reference values of 90.7 pA and 288 mV. The proposed block uses proper addition of CTAT and PTAT curves, resulting in an excellent temperature coefficient of 15.2 ppm/°C and 36.8 ppm/°C for compensated current and voltage values, respectively, at a nominal supply of 0.5 V for a wide temperature range of −55 °C to 100 °C. Usage of gate leakage transistors in place of resistors helps in reducing the power and area of the circuit to 0.087 mm2. The circuit is implemented in 90 nm technology and operates effectively across a wide voltage range of 0.5 V–2.6 V with a supply sensitivity of 0.028 %/V and 0.154 %/V for current and voltage reference, respectively. The entire circuit takes a power of 275.26 pW at nominal conditions.

Abstract

Various studies have shown the advantages of using Machine Learning (ML) techniques for analog and digital IC design automation and optimization. Data scarcity is still an issue for electronic designs, while training highly accurate ML models. This work proposes generating and evaluating artificial data using generative adversarial networks (GANs) for circuit data to aid and improve the accuracy of ML models trained with a small training data set. The training data is obtained by various simulations in the Cadence Virtuoso, HSPICE, and Microcap design environment with TSMC 180 nm and 22 nm CMOS technology nodes. The artificial data is generated and tested for an appropriate set of analog circuits and digital cells. The experimental results show that the proposed artificial data generation significantly improves ML models and reduces the percentage error by more than 50% of the original percentage error, which were previously trained with insufficient data. Furthermore, this research aims to contribute to the extensive application of AI/ML in the field of VLSI design and technology by relieving the training data availability-related challenges.

Abstract

In this paper, a cost-effective and easy-to- implement auto-trim technique is introduced for PTAT or CTAT resistance based current references. The resistance with a process-insensitive temperature coefficient requires only a single point trim at room temperature, achieving process and temperature-insensitive current. The approach utilizes a data comparison method where on-chip current data is compared with off-chip reference data to trim the resistance of the current reference. The off-chip reference data is generated using a low-cost external resistor that is used only during the trimming operation. The proposed trimming sensor effectively calibrates the current, offering precision close to manual trimming, leading to cost, time, and resource savings. To validate the working of the proposed technique, the auto trim sensor with on-chip current reference is designed in TSMC 180nm technology. The auto trim sensor calibrates the on-chip current from ±25% (due to voltage and resistance process variation) to ±1.5% across the process and 3σ mismatch

Abstract

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Abstract

A constant reference voltage/current generating circuit connected between a power supply voltage source and a ground that provides a constant reference voltage/current at an output terminal. The constant reference voltage/current generating circuit includes one or more transistors that generates the constant reference voltage by determining a difference between a gate-source voltage of a first transistor and a gate source voltage of a second transistor with respect to a temperature. The constant reference voltage is mirrored at the output terminal of the constant reference voltage/current generating circuit using a current mirror circuit. The current mirror circuit is connected to the constant reference voltage/current generating circuit.

Abstract

An on-chip resistance amplifier which amplifies the resistance of a small on-chip resistor in die size is provided. The amplifier is a two-terminal circuit of which a high voltage terminal ranging from 0.4 Volts to 3.6 Volts and a second low voltage terminal at the ground includes a small on-chip resistor, a Voltage divider, an operational amplifier op-amp, a NMOS transistor. The voltage divider works in ultra-low power. The voltage (V) at high voltage terminal is divided by some gain A which is V/A, a second voltage. The second voltage is given to the on-chip resistor R. The current generated by on-chip resistor is passed through the higher voltage terminal and the resistance seen at the higher terminal is the amplified resistance of A*R.

Abstract

Biomolecules play indispensable roles in all life processes, including disease development, so their accurate detection is critical to cell investigation, medical diagnosis, and treatment. Radio Frequency (RF) sensing has become a popular testing technique compared to traditional methods for biomolecule analysis, providing results in less time using less volume of samples. It allows rapid, sensitive, real-time measurements and label-free techniques. However, for taking the signals from biomolecules over the RF-based sensors we need to connect them with the Vector Network Analyzer (VNA) which is a bulky and costly device. To develop an RF sensing based a true lab-on-chip (LoC) device, the paper presents a fully integrated low-power less-area on-chip single port CMOS VNA designed in 65nm CMOS technology to detect the bio-molecule The proposed design works in a tunable frequency range of 0.5 GHz to 2.5 GHz, ensuring much higher precision. Using an RLC equivalent of an Interdigitated capacitor (IDC) sensor, a fully integrated architecture for detecting $S_{11}$ of the biomolecules has been introduced. A resistive bridge coupler is used for wideband operation with a directivity of 14.89dB up to 2.5 GHz. Also, a high-linearity LNA (low noise amplifier) is designed with a linearity of -13dB and a gain of 14dB. The LNA has a low NF of 3.21dB. The design occupies an active area of 0.01767mm^2 and consumes power of 41mW from a 1 V supply.

Abstract

Aggressive scaling down of transistor dimensions has made process-aware circuit modeling a crucial task. Achieving accurate circuit modeling requires lengthy and resource intensive simulations. Machine Learning-based surrogate models, offering computational efficiency and speed, are viable alternatives to traditional simulators. This paper introduces a meta-learning approach designed to accurately capture process induced variations in the leakage power of VLSI circuits. The impact of a wide range of fluctuations in operating conditions, including temperature (-55°C to 125°C) and supply voltage (±10%) has also been incorporated for leakage modeling. The proposed meta-learning model is versatile, enhancing the performance of underlying baseline machine learning models while eliminating the need for time-consuming hyperparameter optimization. Our experiments on leakage estimation using 16 and 7 nanometer FinFET technology nodes demonstrate an average improvement of up to 50% and 48% in Mean Absolute Percentage Error compared to stand-alone baseline models.

Abstract

Generative AI has seen remarkable growth over the past few years, with diffusion models being state-of-the-art for image generation. This study investigates the use of diffusion models in artificial data generation for electronic circuits to enhance the accuracy of subsequent machine learning models in tasks such as performance assessment, design, and testing when training data is usually known to be very limited. We utilize simulations in the HSPICE design environment with 22nm CMOS technology nodes to obtain representative real training data for our proposed diffusion model. Our results demonstrate the close resemblance of synthetic data using diffusion models to real data. We validate the quality of generated data and demonstrate that data augmentation is certainly effective in the predictive analysis of VLSI design for digital circuits.

Abstract

This paper proposes a low-power relaxation oscillator for low-power high-temperature IoT systems. It generates a 959 Hz clock signal from −40 to 170°C, consuming 6.75 nW at 0.65 V. A proposed switch-leakage compensation scheme nullifies the effects of body diode and subthreshold leakages on oscillator output frequency at high temperatures, thereby obtaining a wide operating temperature range. The oscillator implemented in a 180 nm CMOS process achieves a temperature coefficient of 40 ppm/°C from −40 to 170 °C at 0.65 V and a line sensitivity of 0.5 %/V from 0.65 to 2.4 V at room temperature, in simulation. Compared with state-of-the-art sub- μW oscillators, this circuit obtains the highest operating temperature and the maximum temperature range.