Abstract

This paper presents a low power voltage reference and current reference in one circuit. The reference voltage is the sum of the complementary to absolute temperature (CTAT) gatesource voltage of a MOSFET operating in the subthreshold region and a scaled version of the proportional to absolute temperature (PTAT) ΔVGS of two MOSFETs operating in subthreshold region. The generated temperature independent reference current is the ratio of the reference voltage and a resistance. The proposed circuit does not use an operational transconductance amplifier (OTA) to generate the reference current, thereby eliminates the variation in current due to any offset of the OTA. Furthermore, the circuit uses a native MOSFET for ameliorating the DC PSRR. The proposed circuit is designed in a 130nm CMOS process. The circuit works with a minimum supply voltage of 1.2V while generating a reference voltage of around 0.7V and a reference current of around 100nA. A TC of 100 ppm/˚C for the reference voltage and a TC of 108 ppm/˚C for the reference current are noted for mismatch and process variations from Monte-Carlo simulations for 300 samples. The circuit consumes only 240nW of power, which makes it suitable for ultra-low power applications.

Abstract

—This paper presents a sub-1V, 593 pA current reference without using resistors and amplifiers. Temperature compensation is achieved by incorporating a CTAT gate to source voltage and a PTAT drain to source voltage in an NMOSbased sub-threshold biased circuit. The proposed architecture achieves ± 3σ/µ process variation of ± 0.75%, which enables seamless trim-free operation. Implemented in the 90nm CMOS process, the temperature-compensated current reference achieves a temperature coefficient of 378 ppm/oC over a high-temperature range of -40 to 100 oC and a line sensitivity of 0.198%/V in a supply voltage range from 0.8 to 2.5 V. Duty cycling technique is adopted in the CTAT generator to reduce the total average power consumption. The proposed circuit occupies an area of 0.074 mm2 while consuming only 3.3 nW at a typical corner of 27 oC and 0.8 V supply.

Abstract

This paper presents a trim-free, low-power, and high-precision voltage/current reference for IoT and biomedical applications. The voltage reference is generated by the proper addition of CTAT and PTAT voltages, whereas, the current reference is generated using a MOSFET in the active region, which acts like a resistor and helps in lowering power consumption without increasing the form factor. Implemented in the 90nm CMOS process, the proposed voltage/current reference outputs a voltage and current of 820mV and 3.23nA, respectively. Without trimming, the process variation of the proposed voltage/current reference is 1.34%(σ/μ) / 1.75%(σ/μ) and the temperature coefficient of the voltage/current reference is 62ppm/oC / 332ppm/oC over the temperature range of -40oC to 100oC. The line sensitivity of the voltage/current reference is 0.296%/V / 0.414%/V for a wide supply range of 1V - 3.5V. The area occupied by the total circuit is 0.0112mm2, while the total power consumption of the design is 37nW at the typical corner of 27oC and 1V supply.

Abstract

Generative AI has seen remarkable growth over the past few years, with diffusion models being state-of-the-art for image generation. This study investigates the use of diffusion models in generating artificial data generation for electronic circuits for enhancing the accuracy of subsequent machine learning models in tasks such as performance assessment, design, and testing when training data is usually known to be very limited. We utilize simulations in the HSPICE design environment with 22nm CMOS technology nodes to obtain representative real training data for our proposed diffusion model. Our results demonstrate the close resemblance of synthetic data using diffusion model to real data. We validate the quality of generated data, and demonstrate that data augmentation certainly effective in predictive analysis of VLSI design for digital circuits.

Abstract

This paper proposes a 162nW resistance-to-digital converter (RDC) for miniature battery-powered sensing systems. The RDC first converts input resistance to a pulse by charging a capacitor to a threshold voltage with a current proportional to the resistance. It compensates temperature sensitivity of the charging current by generating the threshold voltage with the same temperature dependency. Then, the circuit digitizes the pulse using an up-down counter that cancels temperature-dependent delay and offset of the low-power comparator in a digital Correlated Double Sampling (CDS) style. Designed in a 180 nm CMOS process, the proposed circuit achieves a figure-of-merit (FoM) of 0.845pJ/c.s. in simulation, with a conversion time of 50 ms for input resistance from to , while consuming 162nW at a supply voltage of 900 mV. Also, it obtains a temperature sensitivity of 26.9ppm/°C from −40 to 100°C

Abstract

This paper proposes a switched-capacitor network (SCN) based fractional bandgap voltage reference (BGR) circuit designed in 180nm CMOS process to achieve high accuracy and low power consumption for implantable biomedical applications. The design proposes a VEB generator that employs a 2x charge pump and an improved SCN to generate a temperature inde-pendent reference voltage (VREF) ’. A low-power clock generator circuit is proposed, which reduces the leakage current by 37 % compared to previous works, thereby reducing the circuit's power consumption to 18.5nW at typical conditions. The design works from a supply voltage of 0.5V and has a TC of 74. Sppm/ ∘C over a temperature range of 0−80∘C . The PSRR of the circuit is -62.9dB at 100Hz. Based on the Monte Carlo simulations of 500 samples, we obtain an untrimmed 3σ/μ of 2.6%. The design occupies an active area of 0.027mm

Abstract

This work introduces an ultra low power gm-boosted Colpitts voltage controlled oscillator (VCO) with a transformer based tank operating near 20 GHz. The proposed VCO is implemented in TSMC 65 nm CMOS technology. Through postlayout simulations, it is demonstrated that the proposed VCO exhibits a remarkable figure-of-merit of 196.26 dBc/Hz and achieves a phase noise of -111.21 dBc/Hz at a 1 MHz offset while operating at 19.6 GHz. Additionally, the VCO provides a tuning range of 1.7 GHz (18 - 19.7 GHz) and consumes only 1.2 mW of power from a 1 V supply.

Abstract

The paper presents a 0.5V supply, gate leakage-based current/voltage reference for ultra-low power IoT and biomedical applications. The references are generated by the proper addition of PTAT and CTAT curves, which are obtained by exploiting the traditional architecture of the beta multiplier and using the body biasing effect. Gate leakage transistors replace the resistors to ensure low power and low area. The circuit doesn't involve any Op-Amps avoiding the issues of offset that are prominent in these circuits. Implemented in CMOS 90nm technology, the proposed current (voltage) reference achieves a typical accuracy of 34.6ppm/∘C(29.68ppm/∘C) over a wide temperature range of −55∘C to 75∘C with typical value 63.32pA(0.35V). Excellent line sensitivity of 0.0318%N and 0.0576%N are observed for voltage and current reference, respectively, in a supply range of 0.5V - 2.3V. The area occupied by the total circuit is 0.0096mm2, while the power consumption is 415pW at the typical corner of 27∘C and 0.5V supply.

Abstract

This paper presents a fully integrated ultra- low power trim-free current reference for wide-temperature applications. The proposed circuit doesn’t incorporate resistors, amplifiers, and start-up circuitry. A sub-threshold current-based curvature compensation is utilized to extend the temperature range. A process calibration technique is included to calibrate against process variations. Designed in a 55nm CMOS process for a temperature range of -55◦C to 150◦C, the current reference occupies an active area of 0.00458mm2. It achieves a line sensitivity of 0.06%/V for a supply range of 1.2-3.6V. The current produced is 250pA, with a temperature coefficient of 70ppm/oC at the typical corner.

Abstract

The paper presents a novel nW range gate-leakage-based Sub-Bandgap Voltage Reference (sub-BGR) for low-power and high-temperature range IoT applications. It generates a reference voltage of 336mV without incorporating any resistors and operating for a high-temperature range of −40°C to 150°C and a supply range of 0.7V-4V. In the above temperature and supply ranges, the proposed circuit's power consumption only goes up by 30x and 1.025x times, respectively. Designed in a 65nm CMOS process, the proposed architecture achieves an accuracy of 94ppm/°C. It achieves a line sensitivity of 0.0066%/V for a supply range of 0.7V to 4V and a PSRR of 89dB at DC and 1V supply. The proposed circuit shows a±3σ -inaccuracy of 4.295% without additional trimming circuits. It occupies only 0.0851mm2 area while consuming only 2.3nW at 27°C and 21.74nW at 150°C for a 0.7V supply.