Abstract

A proportional to-absolute-temperature (PTAT) voltage generating circuit connected between a power supply voltage source and a ground for providing a PTAT voltage at an output terminal of the PTAT voltage generating circuit to act as a temperature sensor is provided. The PTAT voltage generating circuit includes a plurality of PMOS transistors. The plurality of PMOS transistors generates a second PTAT voltage by multiplying a first PTAT voltage by a factor equal to a ratio of a first equivalent resistance (R2) and a second resistance (R1) of a first PMOS transistor (M4). The first equivalent resistance (R2) is obtained from a series combination of the plurality of PMOS transistors. The first PTAT voltage is generated by determining a difference between a base-emitter voltage of a first PNP transistor (T1) and the second PNP transistor

Abstract

An Integrated Circuit with an automatically re-tuning analog circuit is provided. The Integrated Circuit comprises (a) an analog circuit comprising a plurality of tunable components each configured to respond to a plurality of change control bits, (b) a Process, Voltage Temperature (PVT) characteristics monitor comprising a plurality of PVT sensors, (c) a tuning memory embedded with a machine learning (ML) model of the analog circuit and (d) an artificial intelligence (AI) engine configured to receive a PVT signal input from the plurality of PVT sensors and the machine learning model embedded in the tuning memory. Each tunable component is configured to change its electrical characteristics such that together each of the tunable components is enabled to retune the analog circuit to attain a predefined set of electrical characteristics.

Abstract

An evident challenge ahead for the integrated circuit (IC) industry is the investigation and development of methods to reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual, timeconsuming, and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-largescale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past toward VLSI design and manufacturing. Moreover, we discuss the future scope of AI/ML applications to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations.

Abstract

Approximate Computing techniques are finding a central role in modern applications, by optimizing architectures to relax some computation but with a constrained inaccuracy. In many applications, the FFT algorithm is invariably applied and there is a need for approximate low energy hardware solutions to the FFT. The paper thus proposes an approximate, fixed-point, in-place, shared memory architecture for FFT. It is well observed that the energy at FFT I/Os is not strictly contiguous, hence the proposed FFT exploits this window to tune the error. The proposed FFT and its associated butterfly unit is constructed to efficiently incorporate approximate Toom–Cook multiplication. As said, a supporting function in error correction based on the sparsity patterns, is a feature of this design. The design synthesized at 32 n m shows on average, a 48.6% and 52.8% improvement in consumption of area and energy, respectively …

Abstract

Various studies have shown the advantages of using Machine Learning (ML) techniques for analog and digital IC design automation and optimization. Data scarcity is still an issue for electronic designs, while training highly accurate ML models. This work proposes generating and evaluating artificial data using generative adversarial networks (GANs) for circuit data to aid and improve the accuracy of ML models trained with a small training data set. The training data is obtained by various simulations in the Cadence Virtuoso, HSPICE, and Microcap design environment with TSMC 180nm and 22nm CMOS technology nodes. The artificial data is generated and tested for an appropriate set of analog and digital circuits. The experimental results show that the proposed artificial data generation significantly improves ML models and reduces the percentage error by more than 50% of the original percentage error, which were previously trained with insufficient data. Furthermore, this research aims to contribute to the extensive application of AI/ML in the field of VLSI design and technology by relieving the training data availability-related challenges.

Abstract

This paper presents a fast and efficient optimization engine with multi-directional, multi-objective algorithms based on a robust transistor sizing approach to improve digital circuit performance. However, such optimization processes are highly simulator-dependent and computationally expensive tasks. There-fore, we propose developing machine learning-based reliable models considering process and operating variations to speed up the optimization procedure by running them on developed Residual Neural Network (ResNN) models instead of running expensive circuit simulations. Results on 22nm Metal Gate High-K digital cells show a reduction in delay and leakage up to 36.7% and 18.8 %, respectively improving computational efficiency by several orders.

Abstract

The technological advancements in healthcare mon- itoring devices, automation, consumer electronics, and soft robotics have resulted in extensive research in flexible pressure, force, and tactile sensors. Piezoresistive sensors are the most widely used flexible pressure sensors due to their low-cost fabrication, high flexibility and simple data-acquisition circuits. In this paper, we report the bending response of a velostat- based flexible pressure sensor by examining its reliability when subjected to repeated mechanical stress. The observed deviation in output voltage was 0.95% for 15 mm, 0.95% for 20 mm, 0.97% for 25 mm, and 2.2% for 30 mm bending radii, for 150 bending cycles, with respect to the flat position. We present a two-parameter (a, b) calibration for the pressure sensor with a fixed bias resistance in the readout circuit. This model can be used to further minimize the deviation due to bending cycles. The results obtained from the experimental research have shown a practical possibility of implementing velostat-based sensors for both static and dynamic flexible systems. Index Terms—Reliability; piezoresistive; pressure sensor; me- chanical stress; velostat

Abstract

The paper presents a low-cost method (no extra LDO, Op-amp) to increase the PSRR of composite pair based temperature sensor. Composite pair is a commonly used circuit to generate a linear PTAT voltage for a wide temperature range. A 180° phase shift, voltage biasing technique is introduced at the gate of the NMOS transistor to obtain a supply independent bias current in composite pair. The proposed technique thus achieves a high supply noise rejection. The circuit as a whole does not require additional circuitry, therefore it saves power and area. A 6μW Temperature sensor with 1mV/°c slope is designed in TSMC 180nm technology and achieves PSRR of -80dB. Post-layout simulation results show that the temperature sensor achieves inaccuracy of ±0.1°C from −55°C to 125°C, PSRR of −80dB at 105Hz and -70dB at 200kHz at 1V power supply, and the line regulation of 0.016%/V in a supply voltage range of 1V to 2.5V. Monte-Carlo simulation result for the output PSRR shows −80.56dB as the mean-value with a maximum deviation of ±1.5dB.

Abstract

The paper presents a sub-nW gate-leakage based voltage and current reference in a single circuit whose reference values are scalable and doesn’t incorporate start-up circuits or resistors in the architecture. The power consumption of the proposed circuit increases by only 2.1x in the temperature range of -55°C to 100°C, unlike conventional voltage/current references where the power consumption increases exponentially w.r.t temperature. Implemented in 90nm technology, the proposed voltage reference (current reference) achieves post-trim typical accuracy of 22ppm/°C(58ppm/°C) and worst-case accuracy of 71ppm/°C(78ppm/°C). Excellent line sensitivities of 0.029%/V and 0.059%/V are observed for voltage and current reference respectively, in a supply range of 1V - 3V. Without any start-up circuit, the observed 99% settling times for voltage and current reference are 1.92ms and 2.526ms respectively. The area occupied by the total circuit is 0.0015mm 2 , while the power consumption is 156pW at typical corner, 27°C and 1V supply.

Abstract

This brief proposes an ultra-low-power current ref- erence in TSMC 180nm technology. Temperature compensation is achieved by taking the ratio of compensated voltage and an on-chip resistance. This design uses the concept of the back- gate effect of critical MOSFET to generate complementary to absolute temperature (CTAT) voltage. The circuit works from a supply voltage of 0.55V and is designed for a reference current of 5.6nA. Furthermore, a pseudo-differential amplifier (PD-AMP) helps realize low line regulation of 0.022%/V in the supply range of 0.55 to 1.9V. An average temperature coefficient (TC) of 256.07ppm/◦C is achieved for mismatch and process variations in Monte-Carlo simulations for 1000 samples over a tempera- ture range of −30◦C to 70◦C. The circuit consumes only 9.5nW of power (at room temperature and minimum supply voltage), making it suitable for ultra-low-power biomedical applications. Index Terms—Peaking current reference, biomedical, sub- threshold region, DIBL, PD-AMP.