Abstract

The paper presents a sub-nW bandgap reference (BGR) that exploits the temperature variation of gate-leakage current in thin oxide devices operating in the accumulation region to generate the reference voltage. The incorporation of gateleakage transistors scales down the power consumption of the BGR to pico-watt level without using any large physical resistors or sophisticated techniques, thereby making it suitable for IoT applications. The BGR is designed in TSMC 65nm technology and occupies an area of 0.009mm 2 . Post layout simulation results show nominal and worst-case accuracies of 23ppm/°C and 44ppm/°C respectively in the temperature range of -40°C to 100°C. Without any trimming, an inaccuracy (±3σ) of 3% is observed for the reference voltage, showing its resilience to process variations. It also exhibits a typical line sensitivity of 0.063%/V in a supply range of 1.5V-3.8V and a PSRR of -65dB at DC and 1.8V supply. The power consumption is observed to be 443pW at 1.5V supply and nominal temperature

Abstract

This paper presents an ultra-low power CMOS voltage reference (CVR) which is free of amplifier and resistor. A current generator circuit is used to generate a supply independent current to bias the active load in the temperature compensation circuit. Drain-source voltage of two critical MOSFETs is made equal in the current generator circuit by using a feedback arrangement to ensure a high PSRR of -75dB for the reference voltage. Temperature compensation is achieved by using the complementary to absolute temperature (CTAT) nature of gatesource of a MOSFET operating in the subthreshold region and proportional to absolute temperature (PTAT) nature of conventional composite pair architecture. The proposed CVR is designed in TSMC 180nm technology. The circuit works desirably for a supply range of 0.85V to 2.3V while generating a reference voltage of around 0.68V. Maximum temperature coefficient (TC) of 184 ppm/˚C and minimum TC of 69 ppm/˚C are noted for mismatch and process variations in the Monte-Carlo simulation for 1000 samples. The circuit consumes only 46nW of power, which makes it suitable for ultra-low power applications. Keywords— CMOS voltage reference, Line sensitivity, Subthreshold region, Temperature compensation.

Abstract

This paper presents an ultra-low power CMOS voltage reference (CVR) which is free of amplifier and resistor. A current generator circuit is used to generate a supply independent current to bias the active load in the temperature compensation circuit. Drain-source voltage of two critical MOSFETs is made equal in the current generator circuit by using a feedback arrangement to ensure a high PSRR of -75dB for the reference voltage. Temperature compensation is achieved by using the complementary to absolute temperature (CTAT) nature of gatesource of a MOSFET operating in the subthreshold region and proportional to absolute temperature (PTAT) nature of conventional composite pair architecture. The proposed CVR is designed in TSMC 180nm technology. The circuit works desirably for a supply range of 0.85V to 2.3V while generating a reference voltage of around 0.68V. Maximum temperature coefficient (TC) of 184 ppm/˚C and minimum TC of 69 ppm/˚C are noted for mismatch and process variations in the Monte-Carlo simulation for 1000 samples. The circuit consumes only 46nW of power, which makes it suitable for ultra-low power applications.

Abstract

The present description relates to a method based on artifi cial intelligence to implement a wide range of microelec tronic circuits that can adapt by themselves to the usage conditions ( e.g. loading changes ) , manufacturing variances or defects ( e.g. process variations , device parameter mis matches , device model inaccuracies or changes , etc. ) , as well as environmental conditions ( e.g. voltage , temperature , interference ) in order to negate all or part of their effects on the circuit performance characteristics and achieve a very tight set of specifications over the wide range of conditions . Each microelectronic circuit is represented by a neural network model whose behavior is a function of the actual input signals , the usage and environmental conditions . An attached AI engine will infer from the model , the input signals , the usage conditions and the environmental condi tions and create the adaptive changes required to modify the microelectronic circuit's behavior to negate all or part of their effects on the circuit performance characteristics and to achieve a very tight set of specifications

Abstract

—The paper presents a sub-nW bandgap reference (BGR) that exploits the temperature variation of gate-leakage current in thin oxide devices operating in the accumulation region to generate the reference voltage. The incorporation of gateleakage transistors scales down the power consumption of the BGR to pico-watt level without using any large physical resistors or sophisticated techniques, thereby making it suitable for IoT applications. The BGR is designed in TSMC 65nm technology and occupies an area of 0.009mm2 . Post layout simulation results show nominal and worst-case accuracies of 23ppm/oC and 44ppm/oC respectively in the temperature range of −40oC to 100oC. Without any trimming, an inaccuracy (±3σ) of 3% is observed for the reference voltage, showing its resilience to process variations. It also exhibits a typical line sensitivity of 0.063%/V in a supply range of 1.5V-3.8V and a PSRR of -65dB at DC and 1.8V supply. The power consumption is observed to be 443pW at 1.5V supply and nominal temperature.

Abstract

This paper deals with transistor sizing based static power optimization for multi-stage CMOS circuits using swarm intelligence algorithm. The overall circuit performance is improved by optimizing the individual basic cell performances. Optimized cells are re-used at places with similar circuit scenarios thereby reducing the number of variables to work with. At each stage of execution, the algorithm generates multiple sizing options for basic cells with varying power-delay specifications to choose from. This work proposes a dual sizing approach for critical and non-critical path cells. The overall process has low circuit dependence and has been applied on a wide range of single and multi-stage circuits (including ISCAS benchmark circuits). The approach considers fabrication process parameter variations (for ±3σ design) in addition to a wide range of temperature (-55oC to 125oC) and supply voltage (±10%) variations for robust sizing solutions. Results show leakage reductions up to 63.6%.

Abstract

In this paper, we aim at optimizing the leakage power and propagation delays using optimization algorithms like Glowworm Swarm Optimization and Neighbourhood Cultivation Genetic Algorithm, subjected to variations in Process, Voltage, Temperature and Aging degradation (PVTA) targeting low power or high performance applications. For high performance applications, we synthesize transistor sizes, at which the critical path delay in worst case PVT conditions with 3 years of NBTI aging degradation is optimized below the critical path delay (of initial sizing) at nominal conditions keeping power budget in bound. On the other hand, for low power applications, we obtain transistor sizing where leakage is reduced by more than 50%, keeping a bound on critical path delay. We have also proposed a step by step optimization method for optimizing complex cells. All the pre and post stress simulations are performed using HSPICE for 22nm Metal Gate High-K dielectric model parameters. The temperature range and the supply voltage ranges are -55 °C to 125 °C and 0.72V to 0.88V respectively. The process parameters are considered at ±3σ variation. The ingenuous working of the circuits for the obtained sizing is ensured by Monte Carlo analysis evaluating over entire range of process variations and operating conditions for the intended life time.

Abstract

The paper presents a sub-nW BJT based temperature sensor for ultra-low power microsystems. The sensor is based on amplifying the difference between base-emitter voltages of BJTs using gate-leakage transistors. Implemented in UMC 65nm technology, the sensor occupies an area of 0.005mm 2 . It achieves a maximum non-linearity error of 0.12°C(3σ) over the temperature range of –55°C to 80°C. Without any trimming, a worst case inaccuracy of +0.36°C/ –1.61°C is observed w.r.t process variations, depicting the process-invariant nature of the temperature sensor. It also achieves a low supply sensitivity of 0.56°C/V over a wide supply range of 0.7V-3V. The power consumption of the sensor is 419pW at 27°C and 0.7V supply.

Abstract

This paper proposes low power optimization using a modified swarm intelligence algorithm for the scenariostransistor sizing based static power reduction and low power standard cell generation for approximate computing. In these scenarios, we explore a lower abstraction level and see how standard cells can be tuned to a power-delay-quality optimal point. For transistor sizing, the algorithm considers fabrication process parameter variations (for ±3σ design) in addition to a wide range of temperature (-55oC to 125oC) and supply voltage (±10%) variations to yield PVT aware robust sizing solutions. The approach has been applied on numerous single and multistage circuits (including ISCAS benchmarks) while proposing a dual sizing solution for non-critical and critical path cells. For approximate systems, we present algorithm-generated full adder designs for speech processing systems. The designs vary in terms of accuracy and power. Results show leakage reductions up to 58.2% for conventional and 66.8% with approximation designs for 22nm metal gate high-K (MGK) technology cells.

Abstract

In this paper, we aim at optimizing the leakage power and propagation delays using optimization algorithms like Glowworm Swarm Optimization and Neighbourhood Cultivation Genetic Algorithm, subjected to variations in Process, Voltage, Temperature and Aging degradation (PVTA) targeting low power or high performance applications. For high performance ap­plications, we synthesize transistor sizes, at which the critical path delay in worst case PVT conditions with 3 years of NBTI aging degradation is optimized below the critical path delay (of initial sizing) at nominal conditions keeping power budget in bound. On the other hand, for low power applications, we obtain transistor sizing where leakage is reduced by more than 50%, keeping a bound on critical path delay. All the pre and post stress simulations are performed using HSPICE for 22nm Metal Gate High-K dielectric model parameters. The temperature range and the supply voltage ranges are −55 °C to 125 °C and 0.72V to 0.88V respectively. The process parameters are considered at ±3σ variation. The ingenuous working of the circuits for the obtained sizing is ensured by Monte Carlo analysis evaluating over entire range of process variations and operating conditions for intended life time.