Abstract

This work presents a highly accurate current reference of 66nA for ultra-low power applications. A very low figure-of-merit (FOM) of 1.3501ppm/°C 2 is achieved on consuming a minimal quiescent current of 199.37nA. To cancel out process variations, the current subtraction technique is employed and a β-multiplier is used to compensate for mobility (μ) and threshold voltage (V th ). In addition, curvature compensation technique backed by PTAT and CTAT current cancellation is adopted to attain a lower temperature coefficient (TC). Hence, an imperceptible variation of accuracy with temperature and supply variations across all process corners is attained. An adopted trimming scheme further minimizes the overall process spread to ±1.515% without compromising on accuracy. Accordingly, a TC of 67.04ppm/°C over a wide temperature range of −50° C to 100° C is obtained. Furthermore, 1.413%/V line sensitivity (LS) in the supply range of 1.38V to 3V is observed. Low power consumption of 275.13nW@1.38V facilitates its use in high-performance low power applications.

Abstract

In this paper, the optimal transistor sizing of the digital cells has been obtained using Simulated Annealing algorithm and an Artificial Bee Colony algorithm and their results have been compared with nominal results for various nanoscale CMOS digital circuits. The goal is to minimize the leakage power keeping the other performance parameters such as propagation delays and the area in the bound. The simulations are done using HSPICE tool for 45nm and below using Metal gate High k Predictive Technology Model cards. To make sure of the unaffected working of all cells in the automotive applications, the temperature range and supply voltage has been taken between −55oC to 125oC and 0.95V to 1.05V respectively. The Overall reduction in leakage power achieved in the logic cells is up to 70% without any penalty in the critical path delay.

Abstract

In this paper, a highly stable all CMOS current reference against temperature and supply variation is proposed. Current reference of 5µA and 50nA has been designed for low power and ultra-low power applications respectively. The reference architecture is based on ratio between the PTAT voltage and the PTAT resistance. The process insensitive temperature compensation is accomplished by dividing TC of voltage with process insensitive TC of resistor. A high PSRR, process independent voltage reference is designed for PTAT voltage. N-poly on chip resistor is used for PTAT resistance. The proposed current reference is implemented in 0.18-µm TSMC technology. The architecture achieved PSRR of 74dB and line sensitivity of 0.05% works at supply voltage variation from 1.4V to 3.6V. The current reference of 5µA and 50nA attain temperature coefficient of 11.6 ppm/oC and 12.2 ppm/oC respectively for the temperature variation of -55oC to 125oC.

Abstract

Enormous increase in process variations (due to progressive CMOS technology scaling) along-with the temperature and supply voltage variations are severely degrading the fabrication outcome of digital circuits i.e. circuits are not accomplishing the specification bounds of the required performances. Therefore, process and operating variations aware optimization has become a very essential task in VLSI design. Moreover, many specifications in a circuit have challenging trade-offs, hence demand effective optimization skills. With this vision, this paper presents optimization algorithm based robust transistor sizing for various nanoscale CMOS digital circuits. The objective is to minimize the static i.e. leakage power without degrading the operating frequency (i.e. keeping the propagation delays in bound) and area. The reported results are shown for 32nm CMOS Metal gate High-k model parameters, however methodology is equally valid for further scaled technology nodes. The Overall reduction in leakage power obtained is up to 88% keeping bound on the critical path delay. The temperature range and supply voltage has been taken between −55◦C to +125◦C (for automotive applications) and 0.90V to 1.10V (±10% variations) respectively at 3-sigma design.

Abstract

With the technology scaling down to sub-50 nm regime, the necessity of process variation aware estimation of Leakage Power is emphasized for robust digital circuit design. Variations in Leakage power results in a large increase in the variation of total power dissipation. This paper presents a Regression based estimation of leakage powers and total power dissipation in nanoscale standard cell-based designs that show an impressive speed-up advantage with respect to analog SPICE-level simulation. We propose a statistical variation aware estimation model through a Multivariate Linear Regression (MLR) and Multivariate Polynomial Regression (MPR) techniques. Exhaustive tests report shows MPR technique outperforms MLR technique in estimating the leakage and total power for the targeted 16 nm CMOS technology with negligible error (<1%). The proposed methodology works as black box i.e. equally valid for 16 nm, 22 nm and 45 nm technology nodes.

Abstract

A sub 1−V , ultra low power temperature sensor has been implemented in TSMC 180 nm. The architecture is digital friendly since it creates a pulse width modulated wave instead of voltage. It uses proportional to absolute temperature(PTAT) characteristics of resistance to generate PTAT delay. Temperature to delay conversion depends only on passive elements, thereby making the circuit insensitive to supply variations. Line sensitivity of 0.23 ◦C/V is achieved for a wide supply range of 0.7−3.6 V . A non linearity error of less than 0.8 ◦C is measured for −55 to 125 ◦C using linear fit curve. This occupies an area of 0.82 mm2 and consumes a power of 47 nW at 0.8 V supply.

Abstract

Due to the advent of deep sub-micron technologies, statistical (in addition to temperature and supply voltage) variations aware estimation of leakages power has become prominent. Also, estimation of leakage currents at SPICE level guarantees the most accurate results, however not feasible means in high complexity ICs. This performs adversely for Monte-Carlo iterations for statistical analysis. In this paper we introduced an accurate machine learning technique to model statistical and operating variation aware estimation from Artificial Neural Network and regression based Multivariate Polynomial Regression which exhibits innately faster computation and attained error less than 1% for the targeted 16nm FinFET technology node although model is black box for any technology. The accuracy of the proposed technique has been tested over several basic cells and estimation of the complex circuits have been carried out utilizing the pre-modelled basic cells.

Abstract

Higher yield, climbing transistor counts and shrinking dimensions of a single Integrated Circuit (IC) have always been the demands in the fabrication market. However, this increased complexity and miniaturization of transistors present a challenge, due to high critical process variations combined with a ubiquitous presence of temperature and supply voltage variations, to achieve the required specification bounds on the desired performance of the circuits. Since optimization has become a very crucial task in IC design, the paper presents an efficient transistor sizing based optimization technique of the CMOS circuits to achieve low power, high performance and high yield design goals. The proposed memetic algorithm judiciously utilizes a threshold based local search procedure to improve convergence in its inherent genetic nature. The algorithm optimizes with the effect of temperature ሾെ૞૞ܗܜ૞૛૚ሿԨ and supply voltage േ૚૙Ψ variations and in addition a number of statistically sampled sets generated as Gaussian, Latin Hypercube and Correlation Screened schemes of process variations. The proposed technique is applicable to any technology node and has been tested over several standard single-stage and some complex multi-stage digital circuits designed using a Multi-Gate high-K dielectric (MGK) 22nm CMOS model. The reduction in leakage power with propagation delay goes as high as ૞૜Ψ with ૢΨ respectively, as observed across the various digital circuits

Abstract

Polar codes have a very good error correcting capacity compared to turbo and LDPC codes of similar length. They are the first to attain the channel capacity. The aim of the proposed work is to design an Area and Power optimal 2b SC polar decoder exhibiting reduced area and power without degrading the latency by iterative decomposition technique. The targeted performances in decoder architecture are achieved by novel reformulation of F-node, G-node and P-nodes.

Abstract

Static power consumption is one of the most critical issues in CMOS digital circuits, and FinFET technology is being recognized as a valid solution for the problem. In this chapter, we utilize a logic-level leakage current estimation technique relying on an internal node voltage-based model. The model is implemented in the form of VHDL packages. By utilizing the capability of the model, the behavior of major leakage component has been analyzed separately for FinFET technology scaling over single- and multi-stage digital standard cells.