Abstract

The goal of this paper is to obtain the robust transistor sizing of the digital logic circuits by minimizing the leakage power keeping the other performance parameters such as propagation delays and area in the bound. To perform such action, Simulated Annealing based Multi-Objective Optimization algorithm has been implemented and further improved the reduction in leakage power using Gradient Descent (MO-SAGRAD).The algorithms are implemented in python and the performance parameters are computed using HSPICE tool at 45nm, 22nmtechnology nodes with Metal Gate High K PTM model cards. Toensure the unruffled functioning of the cells in the automotive applications, the temperature range has been taken between−55oCto125oCrespectively and the supply voltage range istaken as 0.95V to 1.05V for 45nm and 0.76V to 0.84V for22nm technology node. The Overall reduction in leakage power achieved in the logic cells is up to 58% without any penalty in the critical path delay.

Abstract

Fast-computable and accurate leakage models for state of the art CMOS digital standard cells is one of the most critical issues in present and future nano-scale technology nodes. It is further interesting if such model can calculate leakage currents not only at initial circuit life but also over the years based on Bias Temperature Instability (BTI) aging mechanism, which increases the threshold voltage over the years – thus mitigating leakage – but in turn degrades circuit speed. A reliable quantification of such aging-induced leakage mitigation opens the way to effective trade-off techniques for compensating speed degradation while maintaining leakage within specification bounds. The presented logic level leakage characterization and estimation technique, currently implemented as VHDL packages, shows more than 103 speed-ups over HSPICE circuit simulation and exhibits less than 1% error over HSPICE. We report BTI aging aware leakage current estimation for ten years at 25 °C and 90 °C in 16 nm CMOS technology, and we analyze how such leakage reduction trend can be traded off to improve the degraded circuit speed over time.

Abstract

This work focuses on circuit level technique that achieves high swing in single ended output differential amplifiers like differential amplifier with active current mirror load, telescopic cascode, folded cascode etc. This technique is designed in such a manner that it can be visualized as a 2-terminal black box. Now, these 2-terminals can be connected to the conventional single ended differential amplifiers enhancing their swing without degrading other parameters like gain, bandwidth, CMRR etc. This black box achieves its performance consuming less power and minimum circuitry area. All the simulation characterization and validation has been made through UMC 180 nm technology node in Cadence.

Abstract

In this paper, two one-bit full adder design techniques are explored for reduced power consumption in standby mode. The proposed algorithm based techniques compute optimal transistor sizing for variable operating conditions (temperature, supply voltage) to achieve desirable leakage power and speed for a full-adder circuit. Both techniques use ‘SLEEP’ signal to drive full adder circuit to lower standby mode leakage state without even degrading the performances in active mode. The investigation has been carried out for 45 nm, 32 nm, 22 nm Metal Gate High-K PTM models and all the simulation characterizations are carried out using HSPICE simulation tool. Performance comparison of both techniques after optimization has been done over a complete range temperature (−40 ∘ C−125 ∘ C) and ±5% variation in supply voltage. The resultant designs are tested on large full-adder based digital circuits to analyze the reduced standby leakage power. The results show that up to 97% of standby leakage reduction can be obtained with (0.4–15)% delay overhead using the proposed methods of full-adder design.

Abstract

We present the detailed results of the application of mathematical optimization algorithms to transistor sizing in a full-adder cell design, to obtain the maximum expected fabrication yield. The approach takes into account all the fabrication process parameter variations specified in an industrial PDK, in addition to operating condition range and NBTI aging. The final design solutions present transistor sizing, which depart from intuitive transistor sizing criteria and show dramatic yield improvements, which have been verified by Monte Carlo SPICE analysis.

Abstract

Voltage noise can lead to various errors such as dynamic and permanent, which are directly associated to circuit-level reliability issues. Variability in process parameters directly affects the probability of failures associated to voltage noise. Yet, the evaluation of the probability of failures by SPICE level Monte Carlo simulation is prohibitively time-consuming. This work proposes a technique to characterize the input noise and process variations in order to estimate failure probability in a logic circuit path composed of combinational cells and registers. The method allows to correctly estimate the order of magnitude of the probability of failures and to evidence the influence of process variations, while reaching >104 speedup versus SPICE.

Abstract

Aging phenomena, on top of process variations along with temperature and supply voltage variations, translate into complex degradation effects on the required performance and yield of nanoscale circuits. The proposed paper focuses on the development of mathematically optimal circuit sizing for yield maximization on the case study of a CMOS full adder circuit. The final cell design is robust against NBTI aging effects, impact of statistical (global and mismatch) and operating variation of temperature and supply voltage. Monte Carlo analysis has been carried out to verify the estimated yields. The demonstrated technique can be extended to a library of optimally designed digital cells