Abstract

No Results Found

Abstract

In this paper, utilizing the feature of the sonority, the problems of detecting the syllable nuclei and the syllable boundaries are explored. As there is minimal obstruction in the oral cavity in the production of sonorant sounds, sonority feature is used. A method is proposed for extracting the sonority profile from the strength of the dominant resonance frequency using the zero time windowing method. The strength of the dominant resonance frequencies in the specific band of 500 Hz to 1700 Hz is used. The proposed method is evaluated on SVL-DD-NEWScorpora. The results are compared with the Fourier transform method and the energy-based method of extracting the sonority profile. The proposed method performed better compared to other methods, especially in the presence of noise such as white, pink and babble. The method is also evaluated on TIMIT test database and the performance is on par with the current methods in detecting the syllable nuclei.

Abstract

In this paper, we propose a hybrid CPU+GPU data structure, that optimizes search operation for frequently accessed search keys. This is based on the working-set structure due to Badiu et al. [1]. The main idea is to maintain a dynamic set of most frequently accessed keys in the GPU memory and the rest of the keys in the CPU main memory. Further, search queries are processed in batches of size 1K to 16K (K = 210). We measured the query throughput of our data structure using Millions of Queries Processed per Second (MQPS) as a metric, on different key access distributions. On distributions, where some keys are accessed more frequently than others, we achieved 2x higher MQPS when compared to a highly tuned hash map provided by C++ BOOST library, and 1.5x higher MQPS against the B+ tree implementation in the Rodinia GPU benchmark. We further showed the effectiveness of our structure, when it is used to store visited vertices information in breadth-first search traversal of graphs. Here, we achieved 1.2x and 1.5x speedups when compared to the BOOST hash map and the GPU B+ trees respectively.

Abstract

This paper proposes low-power design of the Gaussian-Minimum Shift-Keying (GMSK) demodulator using baseband quadrature signals. High-level architecture of this demodulator incorporates CO-ordinate Rotation-DIgital Computer (CORDIC) engine to accept the in-phase and quadrature components from received GMSK signal to generate phase angle and magnitude of the GMSK signal vector at half the sampling frequency thereby reducing the power consumption. Additionally, the design of differentiator and synchronizer for the suggested GMSK demodulator has been carried out. The proposed demodulator is implemented in field-programmable gate-array (FPGA) and post-route simulated for functional verification. Thereafter, BER performance analysis of this design has been carried out in Additive White Gaussian Noise (AWGN) channel environment. Finally, the suggested architecture is synthesized and post-layout simulated using 90 nm CMOS technology node. It occupies a core area of 0.12 mm 2 with 17770 gates and consumes 4.42 mW at 167 MHz of clock frequency.

Abstract

The significance of anomaly detection is increasing as a result of the rapid increase in unknown attacks. With the increase in deployment of scalable web services, there is a need for developing a scalable anomaly detection mechanisms. In this paper, we propose a scalable anomaly-based Bot Detection Architecture (BotD) in which different anomaly-based bot detection algorithms can be implemented. Our architecture leverages NF scalability provided by Network Function Virtualization (NFV), and network programmability provided by Software Defined Networking (SDN). We have also proposed a loss-free state transfer technique across NFs. We have simulated our architecture using Mininet and Ryu controller, and tested the functioning of the architecture.

Abstract

This paper presents new system-level design for the cognitive sensor based on energy detection to boast the performance accuracy by maintaining a queue of energy samples and computing their average to determine the decision threshold. Thereafter, these values summed over average number of samples are again compared with the recent energy value to decide whether the spectrum is occupied or unoccupied more accurately. The performance of such technique is evaluated analytically for various decision thresholds. Such evaluations indicate that the some advancements made to the energy detection algorithm has demonstrated improvements in the spectrum sensing accuracy under varying signal to noise ratio (SNR) values. Subsequently, we have shown the benefits of the proposed scheme in increas- ing the agility of cognitive radio systems. The performance is measured by using the receiver operating characteristic (ROC) curves under varying number of levels for different SNR values like: -5 dB, -10 dB, -15 dB and -20 dB. With small tradeoffs between the detection probability and the false alarm probability, the scheme improves the spectrum sensing ability greatly in low SNR situations when tested with 10, 100, 1000, 10000 and 100000 samples. Thereby, enhancing the performance of such hardware friendly sensors under low SNR has been a potential achievement of our work. Finally, field-programmable gate-array (FPGA) prototyping of the proposed sensor architecture has been carried out and it has a latency of 21760 nS. Index Terms—Digital Design, FPGA, cognitive radio, detection probability, spectrum sensing and energy detection

Abstract

MIL-STD-1553B data buses are in use in almost all aircrafts and many ground-based military vehicles. But, present day aircraft equipments have much higher bandwidth requirements compared to what is offered by 1-Mb/s legacy 1553 system hardware. A complete rewiring would result in the aircrafts being non operational for a long time, in addition to its high cost of implementation. Instead, only the obsolete MIL-STD-1553 system-on-chip integrated circuits can be substituted to extend their functionality to higher data rates. In this work, we describe the operating principle and implementation of a low power transceiver upgrade which effectively equalizes a 1553 channel across the whole 100-MHz spectrum. Implemented in 0.18μm, this transceiver upgrade circuit achieves a BER of < 10 −16 over a 300-ft 1553 bus while receiving 100-Mb/s data, with a total power consumption of 31.7 mW from a 3.3-V supply.

Abstract

In this paper we present a novel low power 6-bit Flash analog-to-digital converter design using charge steering amplifier for RF applications. The architecture and performance of the designed ADC is described in detail and compared with conventional and other Flash ADCs. The proposed design offers lower power consumption by using a charge-steering amplifier based comparator; the power supply voltage is 0.7 V minimum which makes this design adaptable to wide variety of RF based System-on-Chip (SoC) applications. The ADC is designed in 28nm standard CMOS process with operating sampling frequency of 1GS/s and the performance parameters DNL and INL are ±0.3 LSB and ±0.35 LSB respectively, spurious-free dynamic range (SFDR) is 39 dB, signal-to-noise and distortion ratio (SNDR) is 37.15 dB, effective number of bits (ENOB) is 5.88 bits, power consumption is 3.57 mW @ 0.7 V supply voltage and FOM is 60.6 fJ/conversion-step.

Abstract

Opportunistic reuse is a need based sourcing of software modules without a prior reuse plan. It is a common tactical approach in software development. Developers often reuse an external software module opportunistically to improve their productivity. But, studies have shown that this results in extensive refactoring and adds maintenance owes. We assert this problem to the mismatches between the software under development and the reused external module; caused because of their different assumptions and constraints. We highlight the problems of such opportunistic reuse practices with the help of a case study. In our study, we found issues such as unanticipated behavior, violated constraints, conflict in assumption, fragile structure, and software bloat. In this paper, we like to draw attention of the research community to the wide spread opportunistic reuse practices and the lack of methods to pro-actively identify and resolve the mismatches. We propose the need for supporting developers in reasoning before reuse from the perspective of identifying and fixing both local and global mismatches. Furthermore, we identify other opportunistic software development practices where similar issues can be observed and also suggest the research areas where further investigation can benefit developers in improving their productivity. Copyright © 2016 John Wiley & Sons, Ltd.

Abstract

The purpose of this paper is to present the model of a Humanoid robot inspired by Poppy, modified for heavier load capacity and the balancing of humanoid in multiple work environments. The design has been modified in order to use MX-64 servos with more torque capacity than MX-28 servos which were used in original design. We have also redesigned the ankle joint and feet to make it a more accurate human like model. We are using an integrated approach using zero moment point (ZMP) with force sensing resistor (FSR) and center of mass (CoM) to find balance margins of the robot. Balancing and forward bending experiments on robot are conducted by providing some basic motion to the robot and ensuring that the robot is balanced and moving within safe margins using this approach.