Abstract
Since FCC had authorized UWB frequency range from 3.1 GHz to 10.6 GHz for wireless communication, several technologies developed for communication applications. And, demand of low cost, high data rate wireless communication systems rapidly increased. Although, current wireless design circuits built for cellular or non-cellular applications, trade-off with matching, signal detection, linearity, gain and noise parameters.
In wireless receiver systems, effect of noise of all the subsequent stages is reduced by the gain of low noise amplifier (LNA) and its noise injects directly into the receiver. Thus, it is necessary to boost the desired signal power while adding as little noise and distortion as possible so that the retrieval of this signal is possible in the later stages in the system. As LNA is first block in receiver chain, it must provide high gain for the next blocks. Moreover, noise of LNA is critical, since the received input signal is extremely weak and can be easily corrupted by even small amount of thermal noise. Additionally, it is desirable to integrate the circuit with CMOS technology to achieve low cost and chip area. This block has the job of matching the antenna input with the rest of the circuitry and simultaneously amplifying it for further processing.
Recent demonstrations show that LNAs ranging from few MHz to 10 GHz are included in wireless receivers which uses single LNA for contiguous broadband signal processing. And, there are various techniques to design narrow band and wide band LNAs such as design using basic common source and common gate configurations with few improvement methods such as using noise cancellation techniques.
In contrast to existing LNA topologies implementing noise cancellation techniques which usually do not consider much about gain improvement, this work proposes a design of common gate LNA employing a noise cancelling technique which not only reduces the noise but also improves the gain and is novel to best of our knowledge. In order to cancel the dominant thermal noise, we have analyzed the noise contributions from both, active and passive components in an existing CG LNA. The input matching device viz. first CG transistor was identified as the most dominant
noise source which contributes 42% of overall LNA noise and remains flat i.e. (2.8 ± 0.3) dB over the entire range. However, second stage common source transistor contributes 22% in whole range and is more near the corner frequencies which is due to the narrow band characteristics of common source amplifiers. Hence, this work’s target is to cancel the most dominant thermal noise through proposed noise cancelling technique.
The proposed technique is based on combining two paths one with reversed phase noise-signal and the other with non-reversed phase noise-signal, simultaneously the RF-signals in the two paths should be in-phase. The two parallel paths were designed by symmetrical cascade combination of CG-CS and CS-CG stages. Moreover, theoretical model of noise cancellation is presented along with the derived equations of overall noise figure. Finally, implementation is done using TSMC 0.18 μm CMOSRF technology on Cadence Spectre RF tool. Significantly, proposed LNA achieve a reduction of 22.49% in base noise figure and 31.48% improvement in peak power gain when compared to LNA without noise cancelling technique. Ultimately, peak power gain of 28.4 dB and base NF of 3.17 dB with good stability and linearity are achieved over the spectrum from 2.5 GHz to 4.5 GHz.
Additionally, this work implement a design of UWB LNA which include interstage matching network to carry forward desired signal with the stoppage of undesired signal. Also includes a Chebyshev band pass filter for input matching and a shunt-series inductive peaking network to compensate the gain roll-off at higher frequencies. This design provides a peak power gain of 17.12 dB and base noise figure 3.4 dB within the frequency range from 3.1 GHz to 10.6 GHz. Also demonstrate a good input matching i.e. well below -10 dB in the desired frequency range. The entire circuit consumes 11.2 mW with 1.8 V supply and occupies 1 mm x 0.9 mm of layout area. Moreover, a detailed survey of various existing methodologies (basic and advanced) for narrow band, wide band and noise cancelling LNAs are discussed with their pros and cons.