Abstract

The area of graph mining deals with mining frequent subgraph patterns, graph classication, graph clustering, graph partitioning, graph indexing and so on. In this thesis, we focus only on the area of frequent subgraph mining and more precisely on maximal frequent subgraph mining. MARGIN is a maximal subgraph mining algorithm that moves among promising nodes of the search space along the “border” of the infrequent and frequent subgraphs. This drastically reduces the number of candidate patterns in the search space.

Abstract

Contracts play a major role in establishing binding relationships between various business units and also between businesses and their customers. A contract consists of numerous activities that have to be carried out by the involved parties and contract clauses that address specific concerns in the business process interaction. An e-contract is a contract modeled, specified, executed and deployed (controlled and monitored) by a software system (such as a workflow system). As contracts are complex, their deployment is predominantly established and fulfilled with significant human involvement. This necessitates a comprehensive framework for generic fulfillment of e-contracts. So, the goal of e-contracting is to transform a traditional contract document into an executable e-contract.

Abstract

The rapid increase in the performance of graphics hardware have made the GPU a strong candidate for performing many compute intensive tasks, especially many data-parallel tasks. Off-the-shelf GPUs are rated at upwards of 2 TFLOPs of peak power today. The high compute power of the modern Graphics Processing Units (GPUs) has been exploited in a wide variety of domain other than graphics. They have proven to be powerful computing work horses in various fields. We leverage the processing power of GPUs to solve two highly compute intensive problems: Singular Value Decomposition and Ray Tracing Parametric Patches. Singular Value Decomposition is an important matrix factorization technique used to decompose a matrix into several component matrices. It is used in a wide variety of application related to signal processing, scientific computing, etc. However, little work has been done to implement Singular Value Decomposition on parallel architectures. Direct ray tracing of parametric patches provides high geometric precision resulting in less artifacts and results in better rendering using true normals for lighting at every pixel. Researchers have developed algorithms to ray tracing parametric surfaces directly, but these algorithms are either computationally expensive or have other disadvantages. Both these problems are both computationally demanding and amenable to massively parallel implementations. Singular Value Decomposition computations requires factorizing a dense matrix into component matrices. Finding the intersection of a ray with a B´ezier patch requires finding the roots of a 18 degree polynomial. They require enormous number of floating point operations. The advent of GPUs with support for higher precision and their ever-growing amount of parallel horsepower makes them a tempting resource for such numerical computations. We propose parallel implementations for these problems on a GPU. They outperform the best CPU implementations available significantly. We implement the Singular Value Decomposition of a dense matrix on GPUs using the two step Golub Reinsch algorithm. In the first step, bidiagonalization decomposes a given dense matrix into bidiagonal matrix and component orthogonal matrix using a series of Householder transformations. In the next step, diagonalization is performed by applying the implicitly shifted QR algorithm which takes O(n) iterations. It decomposes the bidiagonal matrix into a diagonal matrix and orthogonal matrices. Each householder transformation reduces a row-column pair. We divide the number of householder transformations required into n=L blocks. L householder transformations are applied in parallel by mapping them to CUBLAS operations to derive maximum performance. We thus, exploit the underlying hardware to the maximum. We use a hybrid implementation for the diagonalization step that splits the computations between the CPU and the GPU. Every iteration of the QR algorithm applies Givens v vi rotations on the elements of the bidiagonal matrix and the corresponding inverse rotations are applied on the rows of the orthogonal matrices which are initially identity. Transformation applied on each row depends on the previous row and transformation applied on it, thus making computations on every row independent. Rotations on the elements of the bidiagonal matrix are applied on the CPU. The inverse transformations are performed on every row in parallel on the GPU. We combine the power and functionality of using CUDA and the high performance software libraries available with it to exploit the GPU parallelism and achieve high computing performance. This approach can be used for solving other graphics and non-graphics tasks. Our complete Singular Value Decomposition implementation outperforms the MATLAB and Intel R Math Kernel Library (MKL) LAPACK implementation significantly on the CPU.We show a speedup of upto 60 over the MATLAB implementation and upto 8 over the Intel MKL implementation on a Intel Dual Core 2:66GHz PC with NVIDIA GTX 280. We are able to compute the Singular Value Decomposition of very large matrices, upto 14K which is otherwise impossible on the CPU due to memory limitations. The GPUs are limited to single precision numbers, though that is changing with the newer generations. The error due to lower precision was less than 0:001%. We present correct ray tracing of parametric bicubic surfaces on the GPU using Kajiya’s approach without subdividing to the GPU.We use a BVH representation of the patches to remove non-intersecting rays. The process starts with a list of rays to be traced in each frame. The BVH is traversed for each ray to enumerate the potential ray-patch intersections. This method forms a univariate 18-degree polynomial for each intersection and finds its roots using the Laguerre’s method. The real roots are the parameter values at the intersection points. Polynomial formation and root finding for

Abstract

This work is about coverage and exploration with multiple robots, and it especially focuses on the terrains represented as digital elevation models. Our work in coverage utilizes greedy decomposition of terrains on the basis of both visibility and time, and intends to show its merits over the aforementioned approaches. We introduce the notion of coupled metrics which not only enables us to ascertain the ‘goodness’ of a terrain point, but also allows us to provide a reasonable solution to the hitherto un-tackled problem of finding good starting points for the robots. The proposed metric approach also allows us to affect a co-ordinated multi-robot effort, something else which is lacking in existing coverage literature (although there are significant works in 2D exploration literature). We introduce joint allocation strategy variants which ensure that the robots cover efficiently in reduced time or reduced sum of path lengths. The issues of robustness and proper observability are also addressed in subsequent variants of the problem. We provide a methodology that guarantees coverage as long as one of the robots is functional and a visibility model which enforces sufficiency constraints on terrain observability. Our work on exploration deals with both 2D and 3D terrains. A more efficient metric is utilized for choosing the next view point; Extensive simulations both in 2D and 3D, and real world experiments on Pioneer-3DX establish its efficacy over the ones in use now. Moreover, apart from using the previously used synchronous frontier allocation mechanism for multiple robots, we propose an asynchronous frontier allocation strategy; This is shown to be advantageous not only in terms of effectiveness, giving us much better exploration times but also in implementation terms. In 3D, we propose an exploration methodology for UAVs covering terrains represented as heightmaps. We introduce a way for calculating expected visibilities ( expected information gain ) and a way of utilizing information attained from terrain features already explored in deciding the next points of visit.

Abstract

The problem of evaluating software architecture is an important problem of software engineering. The purpose of the architecture evaluation of a software system is to analyze the architecture to identify potential risks and to verify that the quality requirements have been addressed in the design. Different techniques have been developed to evaluate a software architecture. Most common among these techniques are model based approaches, metric based methods and scenario based analysis. Service-Oriented Architecture (SOA) is an architectural approach (or style) for constructing complex software-intensive systems from a set of universally interconnected and interdependent building blocks, called services. Services used in composite applications may be brand new service implementations, they may be fragments of old applications that were adapted and wrapped, or they may be combinations of the above. The emergence of SOA as an approach for integrating applications presents many new challenges to organizations resulting in significant risks to their business. Particularly important among those risks are failures to effectively address quality attribute requirements such as performance, availability, security, and modifiability. Hence, it becomes necessary to evaluate a service oriented architecture based application in the context of quality attributes. In this dissertation, our aim is to investigate the limitations of using scenario based software architecture evaluation approaches in SOA paradigms. We investigate that most of the current approaches in the literature of software architecture, do not consider the factors that are more specific in SOA based applications. For example, to the best of our knowledge, current evaluation approaches do not address the quality issues that arises due to a SOA governance lifecycle. There must be a mechanism to investigate how governance policies are impacting the quality attributes (positively or negatively). We show that a governance lifecycle is a critical element of any SOA based application and must be analyzed in the context of quality attributes. Current software architecture evaluation methodologies also have not been studied and used in the areas of modern cloud based services. In brief, we look at the problem from following different angles: (1) evaluating a SOA governance model; (2) analyzing data security risks in cloud based service environments; and (3) evaluating the attack surface and root cause of an attack in an SOA based enterprise application. Security is considered as the most prominent quality attribute in software applications. Therefore, throughout our work, we primarily focus on security analysis, out of all the quality attributes. The impact of SOA governance mechanism on the organization’s quality attributes is largely not studied or evaluated in a structured manner. To overcome this problem, we propose SAGE (Service Oriented Architecture Governance Evaluation) as a quantitative approach, to evaluate the impact of SOA governance policies on prominent quality attributes. Our approach facilitates an exhaustive quantitative impact analysis to evaluate the effectiveness of SOA governance policies. This can be further used to estimate the current maturity level of any SOA based enterprise. To evaluate the data security risks in cloud based services, we did a survey of prominent security issues in current cloud computing environments. Based on these issues, we propose a risk analysis approach for analyzing the data security risks. This approach can be used by any potential service user, before putting his confidential data into a cloud computing environment. As a solution to the security analysis in SOA based enterprise applications, we present an approach to compute the attack surface in a SOA based enterprise application. We also discuss that how we can map an attack surface from a service layer to a business process layer. Further, we present an approach to investigate the root cause of an attack. This approach can be used directly by any SOA based enterprise to evaluate the security and therefore a possible reduction in security attacks. In our work, we attempt to answer the following questions: (1) Are the existing software architecture evaluation approaches sufficient in service oriented paradigms? (2) If no, what are the areas that remain unexplored? (3) How to address these unexplored areas? Our study brings out some interesting results. We show that evaluation of a SOA governance lifecycle is necessary to estimate the quality and dynamic behavior of the composed application. Our work also unveils various security issues in cloud based service environments. The presented work is an initial attempt to make the SOA evaluation and management more structured and effective.

Abstract

Sentence realisation involves generation of a well-formed sentence from a bag-of-words. Sentence realisation has wide range of applications ranging from machine translation to dialogue systems. In this thesis, we present five models for the task of sentence realisation. The five models proposed are sentential language model, subtree-type based language models (STLM), head-word STLM, part-of-speech (POS) based STLM and marked head-POS based LM. The proposed models employ simple and efficient techniques based on N-gram language modeling and use only minimal syntactic information as dependency constraints among the bag-of-words. This enables the models to be used in wide range of applications that require sentence realisation. We have evaluated the proposed models on two different types of input (gold and noisy). In the first input type, dependency constraints among the bag-of-words are extracted from treebank which is manually transcribed and in the second input type, the dependency constraints among the bag-of-words are noisy as they are automatically extracted from a parser. We have evaluated the models on noisy input in order to test the robustness of our models. From the results, we observed that the models performed well even on the noisy input. We have achieved state-of-the-art result for the task of sentence realisation. We have also successfully tested a graph based nearest neighbour algorithm for the task of sentence realization. We have shown that using the graph-based algorithm, the computational complexity can be reduced from factorial to quadratic at a cost of 2% reduction in the overall accuracy. This method makes our module suitable for employment in several practical applications.

Abstract

The field of electronics has undergone tremendous changes in recent times. The innovations in it have been happening in multiple perspectives, among which the growth of portable computing devices has lead to a new wave of miniaturization and low power development. The rise of high bandwidth internal devices like GPUs (Graphic Processing Units), Multicore processors etc has lead to the growth of high frequency busses like PCI (Peripheral Component Interconnect), the Northbridge/Southbridge FSB (Front side bus) etc. Also the increasing use of multimedia streaming and external storage devices has lead to a massive increase in memory-intensive applications. The need for a simpler protocol has made most of them to be block data transfer systems with the final usage in caches, DMA (Direct Memory Access), Video data transfer etc all tending to be block data transfer utilizing some form of a buffer. I/O pads driving external busses dissipate a major portion of this power as they drive large capacitances, and operate at a higher voltage. This forms a good part of the overall power consumption of a system. In this thesis, a novel technique, Transition Inversion, to reduce power consumption of buffered busses is proposed. This work outlines a data coding protocol by which these transitions can be reduced for block data transfer over buses such as DMA, cache lines etc. Block data transfers generally occur through data buffers. The prior knowledge of the data to be transmitted, when it is stored in the buffer, is exploited in serial fashion to reduce transitions on every bus line. The technique considers a buffer of data to be a collection of bitstreams running in parallel over multiple lines. The transitions are counted in a bit serial fashion and used to determine whether the transitions in any given bitstream have to be inverted. This way the data running on any given line sequentially is encoded such a way it will have a reduced number of transitions. The technique is implemented in an optimized fashion using pipelining so that it can be used in practical systems with only a slight compromise in performance. This is achieved by calculating the decision as the data is being loaded on to the buffer and doing the encoding on the fly. This is one aspect which is lacking in most existing algorithms as they are not amenable to low delay implementation. The critical parameter of delay, which limits bandwidth, is reduced by 64% with the proposed technique and the pipelined implementation. Also the proposed technique and implementation does not require any extra bus lines to be used as is wont with most existing techniques. This does away with the rise in PCB (Printed Circuit Board) fabrication costs. Theoretical analysis of transition inversion showed it to be reducing transitions that is, independent of the increase in bus width. Most existing techniques suffer with increasing bus widths, requiring mitigation factors that themselves increase wiring requirements. Also transition inversion scales slower in hardware complexities compared to another comparable technique which makes it suitable for the increasing data widths in modern busses. The analyses showed that the technique is suitable for modern bus architectures in terms of delay, space complexity and the extra overhead power consumed. It was seen that the bandwidth need not be limited and still a good amount of power saving with the overhead was obtained.

Abstract

Ever since the induction of Integrated circuits into mainstream usage, numerous research efforts have been made into optimizing the circuits implemented on silicon with respect to Power, Area, Time (PAT), and most recently reliability. Due to the recent insurgence of mobile devices, low power design techniques are being given more emphasis. Power dissipated can be reduced at the device, circuit, system architecture, or software design levels. The focus of this work is aimed towards the reduction of power dissipation in electronic systems, by way of using inexact logic in implementing systems, where error can be tolerated, and/or neglected. An inexact logic circuit is constructed by selectively converting minterms/maxterms of its Boolean function into don’t cares. The intuition in doing this is that by converting only a small fraction of minterms/maxterms into don’t-cares, an inexact version of the Boolean function can be synthesized with a significantly lower area-power-delay footprint than the exact Boolean function. Decision making circuits, which are generally sensitive to errors, have been chosen as the subject of analysis. Several applications are presented where inexactness can be applied, and their performance, in terms of power and system accuracy is quantified with varying levels of inexactness. This thesis also outlines a set of general guidelines to design inexact circuits, on a per case basis. To simplify the process, a heuristic framework to generate inexact circuits with varying levels of inexactness has been implemented. The above mentioned applications are classified into 3 categories based on the impact of the decision made, on system accuracy. These categories are: No impact, Tolerable impact, and Significant impact, on system accuracy. For applications with no impact, the only deciding criteria in introducing inexactness are the overall improvement in power and speed. For applications under the tolerable impact category, a system accuracy parameter should also be considered in validating an inexact circuit. For applications with significant impact, inexactness is seldom tolerated, as system accuracy is critical. Bus coding, Median Filter based Image blurring, and Non-Modular Redundancy (NMR), falling under the no impact, tolerable impact, and significant impact categories respectively share the majority voter as a common decision circuit used. A Least Recently Used (LRU)-variant replacement algorithm for Translation Lookaside Buffers (TLB), and a DCT threshold based image blurring process, with the former having no impact on system accuracy and the latter having tolerable impact, share a comparator as a decision circuit. Different inexact versions of these decision circuits are generated and their performance parameters with respect to the applications are measured. A comparison has been made with the levels of inexactness and the power dissipation of the system and the system performance. The results obtained promise a drastic reduction in power dissipation, up to 300%, with tolerable deviation in system accuracy. Although critical path delay was not a parameter for optimization, a gain of up to 30% was observed on this front. The chip area and static power dissipation is also reduced significantly. The results obtained validate the use of inexact logic in applications which are either impervious or tolerant to the errors produced due to the inexactness. This provides a new avenue to low power system design, which can be used in congruence to other circuit design, and system level design techniques.

Abstract

Interconnects play a major role in deep submicron (DSM) technologies such as 90nm and below. While gate delay dominated interconnect delay in earlier technologies, it is no longer the case and delays associated with interconnects are becoming increasingly important. This is because in DSM technologies, interconnect can no longer be seen as a simple resistor but the associated parasitics such as capacitance and inductance also need to be considered. Thus any signal propagating through such an interconnect can be expected to be delayed. Buffer insertion is one popular technique to reduce (eliminate) the delay. In this technique, buffers are placed at regular intervals along an interconnect that seeks to restore the signal each time it is affected by the parasitics. However, buffers themselves have certain switching time that contributes to delay. A large number of such buffers along an interconnect can thus contribute to overall delay to signal propagation. Also buffer switching contributes to power dissipation. Further in DSM technologies, leakage power is a major problem and buffers may consume power even when they are not switching. Thus there is an urgent need to evolve techniques that while reducing the overall delay, also consume lesser power, dynamic as well as static. In this thesis, Schmitt trigger as an alternate to buffer to reduce delay and power in interconnects is examined. The most favorable feature of Schmitt trigger is it’s adjustable threshold voltage, and since it can be controlled, the threshold voltage can be chosen to be above or below Vdd=2 a voltage at which buffer normally operate. Thus a Schmitt trigger can be designed to switch faster than a buffer leading to a reduction in delay. Further, the adjustable low-voltage threshold of the schmitt trigger handles more noise and voltage glitches as compared to buffer. Proposed approach is first implemented for linear interconnects of various lengths and then on buses which are groups of interconnects. It is shown that the proposed approach is better in terms of delay, power and crosstalk noise reduction compared to that of buffers.

Abstract

Blind classification of digital modulations finds applications in defense and software defined radio, and higher-order statistics have attracted lot of attention in this regard. Multipath propagation severely degrades the performance of the blind classification algorithms. Recently, some work has been reported on classification in multipath channels where they perform blind channel estimation based on higher-order statistics, and use the channel estimate in computing the features of interest. However, some of these methods are not applicable to PAM and, 8- and 16-PSK modulations. In our thesis, we consider 9-class problem which includes PAM and PSK constellations and use a blind channel estimation method, in which we combine the magnitude response of the channel obtained from second-order statistics with the phase response derived from higher-order statistics. The channel estimate so obtained is used in computing the required features. Combining these features with the distance metric, we develop an algorithm for hierarchical classification of the underlying modulations. We illustrate the effectiveness of our method in different multipath scenarios using simulations. Specifically, we compare the classification performance obtained using our method of channel estimation with that using higher-order statistics based channel estimation. We also briefy bring out why the higher-order statistics based channel estimation methods, proposed in the context of modulation classification, fail in the above cited PAM and PSK constellations.