Abstract
The rapid proliferation of energy-constrained electronic systems, including IoT nodes, biomedical
implants, and portable devices, has intensified the demand for ultra-low-power and area-efficient analog
circuit design. This thesis presents the design and analysis of advanced ultra-low-power analog building
blocks with a focus on current and voltage references, as well as high-speed comparators, optimized for
energy and area efficiency under wide process, voltage, and temperature variations.
A series of resistorless current and voltage reference architectures are explored, leveraging subthreshold operation and the complementary temperature characteristics of CTAT and PTAT voltages to
achieve robust temperature compensation. A sub-1V current reference generating 593 pA is demonstrated, achieving a temperature coefficient of 378 ppm/◦C over a range of −40◦C to 100◦C, with a line
sensitivity of 0.198%/V across a supply range of 0.8 V to 2.5 V. The design consumes only 3.3 nW at
27◦C and occupies 0.074 mm2
, while maintaining ±0.75% (3σ/µ) process variation, enabling trim-free
operation. Further, an integrated ultra-low-voltage reference operating at 0.5 V generates 90.7 pA and
288 mV current and voltage references, respectively, achieving temperature coefficients of 15.2 ppm/◦C
and 36.8 ppm/◦C. The circuit operates across a wide supply range of 0.5 V to 2.6 V with line sensitivities
of 0.028%/V and 0.154%/V, consuming only 275.26 pW and occupying 0.087 mm2
through the use of
gate leakage-based techniques.
To address line sensitivity and enable operation over extreme temperature ranges, a compact voltage
reference architecture employing only four transistors and a dual-loop regulation scheme is proposed.
The design achieves a reference voltage of 451.6 mV while consuming 37.6 pW, with an ultra-low
line sensitivity of 0.009%/V. It operates over a wide temperature range of −30◦C to 160◦C with a
temperature coefficient of 70.2 ppm/◦C, enabled by threshold voltage modulation and leakage control
techniques.
In addition to reference generation, a 0.3 V bulk-driven rail-to-rail comparator with dynamic transient
enhancement is introduced to overcome the speed limitations of subthreshold operation. The proposed
design achieves a 10× improvement in rise time, with a transient response of 7.56 ns and a bandwidth of
1.07 MHz while consuming only 28 nW of power, demonstrating portability across 65 nm and 180 nm
CMOS technologies.
While the previously presented resistorless architectures demonstrate excellent simulated performance in terms of ultra-low power and compactness, their reliance on device-level characteristics makes
them inherently more susceptible to process variations, potentially impacting yield and long-term reliability. To address these limitations, area-efficient resistance-based current references are investigated
and validated through silicon tape-out measurements. A fabricated design in 0.18 µm CMOS delivers
a 10 nA reference current while consuming 40 nW, achieving a temperature coefficient of 136 ppm/◦C
over −40◦C to 100◦C and a line sensitivity of 1.1%/V across a 1.4 V to 1.9 V supply range, with a compact area of 0.03 mm2
. Furthermore, a low-cost single-point auto-calibration technique is proposed,
enabling compensation of temperature and process variations. The calibrated 1 µA current reference
achieves ±2% accuracy with a temperature coefficient below 150 ppm/◦C over −40◦C to 100◦C, offering performance comparable to conventional trimming methods while significantly reducing calibration
complexity, time, and cost.
Additionally, this thesis presents a fully integrated ultra-low-power and area-efficient RC oscillator based on a resistance amplification technique for compact on-chip timing generation. Implemented
in a 0.18 µm CMOS process, the oscillator synthesizes a large effective resistance using amplified
polysilicon resistor characteristics, significantly reducing silicon area while maintaining frequency stability. Continuous-time offset mitigation techniques are employed to suppress low-frequency noise and
amplifier-induced offsets. The proposed oscillator generates a stable 5 kHz clock from a 1.4 V supply
with ultra-low power consumption, achieving a temperature coefficient of 100 ppm/◦C over −40◦C to
100◦C and a line sensitivity of 1%/V across a 1.4 V to 2 V supply range using single-point calibration.
Overall, the proposed architectures demonstrate significant improvements in power consumption,
area efficiency, temperature stability, and robustness, making them well-suited for next-generation ultralow-power analog and mixed-signal systems.